The invention generally relates to a frequency locked loop.
A frequency locked loop (FLL) typically is used for purposes of generating a signal that is synchronized, or “locked,” in frequency and/or phase to a reference signal. For example, when the FLL is locked, the frequency of the FLL's output signal may be a specified multiple of the frequency of the reference signal; and the output signal may have a specific phase relationship to the phase of the reference signal. A frequency locked loop which also locks the phase of the output signal to the phase of the reference signal is also known as a phase locked loop (PLL).
A conventional FLL may include a voltage controlled oscillator (VCO), which generates the FLL's output signal. The VCO's frequency typically is regulated to achieve lock through the use of a feedback loop, which controls the VCO based on a comparison of the output signal with the reference signal. Often, the output signal and the reference signal are divided in frequency before making the comparison. A typical FLL may include a phase detector that compares the phase of the FLL's output signal with the reference signal and controls a charge pump accordingly. The signal that is produced by the charge pump typically is filtered through a loop filter to produce a control signal that regulates the frequency of the VCO.